Verification by error modeling : using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic

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Publication details: The Hague, London Kluwer Academic Publishers 2003Description: xiv, 216 p. : ill. ; 25 cmISBN:

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Item type: Books

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Current library	Call number	Status	Date due	Barcode
Anna Centenary Library	621.395 RAD (Browse shelf(Opens below))	Available		299784

Includes bibliographical references and index

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