Hsu, Yu-Chin <br/><br/>
VHDL modeling for digital design synthesis 
by Yu-Chin Hsu ... [et al.] 
 - Deventer ; Boston, MA  Kluwer Academic  c1995 
 - xvii, 356 p. : ill. ; 25 cm 
<br/><br/> Includes bibliographical references (p. [323]-326) and index 
<br/><br/><label>ISBN: </label>9780792395973 
<br/><br/><label>ISSN: </label>95020393 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Computer aided design<br/>Digital electronics - Computer simulation<br/>VHDL (Computer hardware description language)
<br/><br/><label>Dewey Class. No.: </label>621.392 HSU