TY  - BOOK
AU  - Radecka, Katarzyna
AU  - Zilic, Zeljko
TI  - Verification by error modeling : using testing techniques in hardware verification
SN  - 9781402076527
SN  - 200306204
U1  - 621.395 RAD 
PY  - 2003///
CY  - The Hague, London
PB  - Kluwer Academic Publishers
KW  - Error analysis (Mathematics)
KW  - Integrated circuits - Verification
KW  - Integrated circuits - Very large scale integration - Computer-aided design
N1  - Includes bibliographical references and index
ER  -