Radecka, Katarzyna <br/><br/>
Verification by error modeling : using testing techniques in hardware verification 
written by Katarzyna Radecka, Zeljko Zilic 
 - The Hague, London  Kluwer Academic Publishers  2003 
 - xiv, 216 p. : ill. ; 25 cm 
<br/><br/> Includes bibliographical references and index 
<br/><br/><label>ISBN: </label>9781402076527 
<br/><br/><label>ISSN: </label>2003062044 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Error analysis (Mathematics)<br/>Integrated circuits - Verification<br/>Integrated circuits - Very large scale integration - Computer-aided design
<br/><br/><label>Dewey Class. No.: </label>621.395 RAD