Logic synthesis and verification 
editors, Soha Hassoun, Tsutomu Sasao. ; consulting editor Robert K. Brayton 
 - Dordrecht ; Boston  Kluwer Academic Publishers  2002 
 - xiv, 454 p. : ill. ; 24 cm 
<br/><br/> Includes bibliographical references and index 
<br/><br/><label>ISBN: </label>9780792376064 
<br/><br/><label>ISSN: </label>2001050362 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Logic circuits - Computer-aided design<br/>Logic design - Data processing
<br/><br/><label>Dewey Class. No.: </label>621.395 HAS