Huang, Shi-Yu <br/><br/>
Formal equivalence checking and design debugging 
by Shi-Yu Huang and Kwang-Ting (Tim) Cheng 
 - Dordrecht ; Boston  Kluwer Academic Publishers  1998 
 - xviii, 229 p. ; 24 cm 
<br/><br/> Includes bibliographical references (p. [211-222) and index 
<br/><br/><label>ISBN: </label>9780792381846 
<br/><br/><label>ISSN: </label>98023993 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Application specific integrated circuits - Design and construction<br/>Electronic circuit design - Data processing<br/>Integrated circuits - Verification
<br/><br/><label>Dewey Class. No.: </label>621.3815 HUA