Design for manufacturability through design-process integration IV : 24-25 February 2010, San Jose, California, United States 
Michael L. Rieger, Joerg Thiele, editors ; sponsored and published by SPIE ; cooperating organization, SEMATECH Inc. (United States) 
 - Bellingham, Wash  SPIE  2010 
 - 1 v. (various pagings) : ill. ; 28 cm 
<br/><br/> Includes bibliographical references and author index 
<br/><br/><label>ISBN: </label>9780819480552 
<br/><br/><label>ISSN: </label>2010283517 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits - Defects - Analysis - Congresses<br/>Integrated circuits - Design and construction - Congresses<br/>Microelectronics industry - Quality control - Congresses<br/>Quality control - Congresses<br/>Semiconductor wafers - Defects - Analysis - Congresses<br/>Semiconductors - Design and construction - Congresses
<br/><br/><label>Dewey Class. No.: </label>620.0042 RIE