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Verification by error modeling : using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic
Publication details: The Hague, London Kluwer Academic Publishers 2003Description: xiv, 216 p. : ill. ; 25 cmISBN:- 9781402076527
- 2003062044
- 621.395 RAD
| Current library | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|
| Anna Centenary Library | 621.395 RAD (Browse shelf(Opens below)) | Available | 299784 |
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| 621.395 PHA Digital logic design and VHDL | 621.395 PUC Basic VLSI design | 621.395 PUC Basic VLSI design | 621.395 RAD Verification by error modeling : using testing techniques in hardware verification | 621.395 REI VLSI : integrated systems on silicon | 621.395 RIE VLSI circuits and systems IV : 4-6 may 2009, Dresden, Germany | 621.395 ROT Fundamentals of logic design |
Includes bibliographical references and index
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