CMOS circuit design, layout, and simulation R. Jacob Baker

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Publication details: Piscataway, NJ ; Hoboken, NJ IEEE Press, Wiley Interscience 2010Edition: 2nd edDescription: xxxiii, 1038 p. : ill. ; 25 cmISBN:

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Holdings
Current library	Call number	Status	Date due	Barcode
Anna Centenary Library	621.39732 BAK (Browse shelf(Opens below))	Available		126380

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Previous	621.3973 KEE DRAM circuit design : fundamentals and high-speed topics	621.3973 TAN Magnetic memory : fundamentals and technology	621.39732 AKT CMOS PLLs and VCOs for 4G wireless	621.39732 BAK CMOS circuit design, layout, and simulation	621.39732 BAL High voltage devices and circuits in standard CMOS technologies	621.39732 CHE Design of low voltage CMOS switched-OPAMP switched-capacitor systems	621.39732 CLE CMOS IC layout : concepts, methodologies, and tools	Next

Includes bibliographical references and index

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