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Formal semantics and proof techniques for optimizing VHDL models Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
Publication details: Dordrecht ; Boston Kluwer Academic Publishers 1999Description: xvi, 158 p. : ill. ; 25 cmISBN:- 9780792383758
- 98045668
- 621.392 UMA
| Current library | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|
| Anna Centenary Library | 621.392 UMA (Browse shelf(Opens below)) | Available | 289978 |
Browsing Anna Centenary Library shelves Close shelf browser (Hides shelf browser)
| 621.392 SHO VHDL for engineers | 621.392 SUD Introductory VHDL : from simulation to synthesis | 621.392 SUT Verilog-2001 : a guide to the new features of the Verilog hardware description language | 621.392 UMA Formal semantics and proof techniques for optimizing VHDL models | 621.392 VAH Verilog for digital design | 621.392 VAH VHDL for digital design | 621.392 VAH Digital design |
Includes bibliographical references (p. [151]-155) and index
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