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Digital timing macromodeling for VLSI design verification by Jeong-Taek Kong and David Overhauser
Publication details: Dordrecht ; Boston Kluwer Academic 1995Description: xxi, 265 p. : ill. ; 24 cmISBN:- 9780792395805
- 95015414
- 621.395001 KON
| Current library | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|
| Anna Centenary Library | 621.395001 KON (Browse shelf(Opens below)) | Available | 289927 |
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| 621.395 YEO Low-voltage, low-power VLSI subsystems | 621.395 ZOB VLSI design environments | 621.395 ZUM Linear circuit design handbook | 621.395001 KON Digital timing macromodeling for VLSI design verification | 621.395028553 KUR Logic synthesis using synopsys | 621.3950285573 MIN Binary decision diagrams and applications for VLSI CAD | 621.3950287 CHE Efficient branch and bound search with application to computer-aided design |
Includes bibliographical references (p. 231-259) and index
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