Digital logic design and VHDL Anuja A Phadke; Subhash M Deokar

By:

Phadke, Anuja A

Contributor(s):

Deokar, Subhash M

Publication details: New Delhi Wiley India 2009Description: xvi, 227 p. : illISBN:

9788126519989

Subject(s):

DDC classification:

621.395 PHA

Item type: Books

Tags from this library: No tags from this library for this title.

Average rating: 0.0 (0 votes)

Holdings
Current library	Call number	Status	Date due	Barcode
Anna Centenary Library	621.395 PHA (Browse shelf(Opens below))	Available		126319

Browsing Anna Centenary Library shelves Close shelf browser (Hides shelf browser)

Previous								Next
Previous	621.395 PAL CMOS current amplifiers	621.395 PAR VLSI digital signal processing systems : design and implementation	621.395 PED Power aware design methodologies	621.395 PHA Digital logic design and VHDL	621.395 PUC Basic VLSI design	621.395 PUC Basic VLSI design	621.395 RAD Verification by error modeling : using testing techniques in hardware verification	Next

Contents: Combinational Logic Design Combinational Logic Circuits Latches and Flip Flops Sequential Logic Design Introduction to HDLs Introduction to State Machines Digital Logic Families Programmable Logic Devices The Memories

There are no comments on this title.

to post a comment.

Digital logic design and VHDL Anuja A Phadke; Subhash M Deokar

Browsing Anna Centenary Library shelves Close shelf browser (Hides shelf browser)

Find us on the map