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Chip design for submicron VLSI: CMOS layout and simulation John P. Uyemura
Publication details: New Delhi Cengage Learning India Private Limited 2006Description: xvi, 411p. : illISBN:- 9788131501955
- 621.395 UYE
| Current library | Call number | Status | Date due | Barcode | |
|---|---|---|---|---|---|
| Anna Centenary Library | 621.395 UYE (Browse shelf(Opens below)) | Available | 303788 |
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| 621.395 TER Op amps: design, application and troubleshooting | 621.395 THO The Verilog hardware description language | 621.395 TRI Field-programmable gate array technology | 621.395 UYE Chip design for submicron VLSI: CMOS layout and simulation | 621.395 UYE Introduction to VLSI circuits and systems | 621.395 UYE Introduction to VLSI circuits and systems | 621.395 VAN Systematic design of analog IP blocks |
Includes index
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