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Verilog digital system design : RT level synthesis, testbench, and verification (Record no. 88532)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00797nam a2200229Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191130s2006##################000#0#eng## |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780071445641 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 NAV |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Navabi, Zainalabedin |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog digital system design : RT level synthesis, testbench, and verification |
| Statement of responsibility, etc | Zainalabedin Navabi |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | New York |
| Name of publisher | McGraw-Hill |
| Year of publication | 2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xvi, 384 p. : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.) |
| 500 ## - GENERAL NOTE | |
| General note | Includes bibliographical references and index |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Electronic digital computers - Computer-aided design |
| Topical Term | Verilog (Computer hardware description language) |
| 991 ## - | |
| -- | 192125 |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Date acquired | Full call number | Accession Number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|
| Anna Centenary Library | Anna Centenary Library | 09.10.2020 | 621.392 NAV | 490500 | 09.10.2020 | English Books |