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Verification by error modeling : using testing techniques in hardware verification (Record no. 88520)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00881nam a2200241Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191130s2003##################000#0#eng## |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9781402076527 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 RAD |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Radecka, Katarzyna |
| 245 ## - TITLE STATEMENT | |
| Title | Verification by error modeling : using testing techniques in hardware verification |
| Statement of responsibility, etc | written by Katarzyna Radecka, Zeljko Zilic |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | The Hague, London |
| Name of publisher | Kluwer Academic Publishers |
| Year of publication | 2003 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xiv, 216 p. : ill. ; 25 cm |
| 500 ## - GENERAL NOTE | |
| General note | Includes bibliographical references and index |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Error analysis (Mathematics) |
| Topical Term | Integrated circuits - Verification |
| Topical Term | Integrated circuits - Very large scale integration - Computer-aided design |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Zilic, Zeljko |
| 991 ## - | |
| -- | 268562 |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Date acquired | Full call number | Accession Number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|
| Anna Centenary Library | Anna Centenary Library | 09.10.2020 | 621.395 RAD | 299784 | 09.10.2020 | English Books |