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VHDL : programming by example (Record no. 430225)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01315nam a2200205Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 191130s2010##################000#0#eng## |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780070499447 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 PER |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Perry, Douglas L |
| 245 ## - TITLE STATEMENT | |
| Title | VHDL : programming by example |
| Statement of responsibility, etc | Douglas L. Perry |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 4th ed |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | New Delhi |
| Name of publisher | Tata McGraw Hill Education Private Limited |
| Year of publication | 2010 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xvii, 476 p |
| 500 ## - GENERAL NOTE | |
| General note | Contents : Foreword Preface Acknowledgments Chapter 1: Introduction to VHDL Chapter 2: Behavioral Modeling Chapter 3: Sequential Processing Chapter 4: Data Types Chapter 5: Subprograms and Packages Chapter 6: Predefined Attributes Chapter 7: Configurations Chapter 8: Advanced Topics Chapter 9: Synthesis Chapter 10: VHDL Systems Chapter 11: High Level Design Flow Chapter 12: Top-Level System Design Chapter 13: CPU: Synthesis Description Chapter 14: CPU: RTL Simulation Chapter 15: CPU Design: Synthesis Results Chapter 16: Place and Route Chapter 17: CPU: VITAL Simulation Chapter 18: At Speed Debugging Techniques Appendix A: Standard Logic Package Appendix B: VHDL Reference Tables Appendix C: Reading VHDL BNF Appendix D: VHDL93 Updates Index About the Author |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | VHDL |
| 991 ## - | |
| -- | 192297 |
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